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myson technology mtv212m64i (rev 0.9) 8051 embedded monitor controller flash type with isp this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. revision 0.9 - 1 - 2000/11/16 features 8051 core, 12mhz operating frequency. 1024-byte ram; 64k-byte program flash-rom support in system programming(isp). maximum 14 channels of 5v open-drain pwm dac. maximum 32 bi-directional i/o pins. sync processor for composite separation/insertion, h/v polarity/frequency check, polarity adjustment and programmable clamp pulse output. built-in self-test pattern generator with four free-running timings. built-in low power reset circuit. compliant with vesa ddc1/2b/2bi/2b+ standard. dual slave iic addresses. single master iic interface for internal device communication. 4-channel 6-bit adc. watchdog timer with pr ogrammable intervals. 40-pin dip, 42-pin sdip or 44-pin plcc package. general descriptions the mtv212m64i micro-controller is an 8051 cpu core embedded device especially tailored to monitor applications. it includes an 8051 cpu core, 1024-byte sram, sync processor, 14 built-in pwm dacs, vesa ddc interface, 4-channel a/d converter and a 64k-byte internal program flash-rom. block diagram p1.0-7 p2.0-2 ,p2.4-7 p3.4-5 x1 p0.0- 7 rd wr ale int1 x2 8051 p3.2-0 rst p0.0- 7 rd wr ale int1 xfr stout hblank vblank hsync vsync hclamp halfv halfh h/vsync control iscl isda hscl hsda ddc & iic interface adc ad0-2 14 channel pwm dac
myson technology mtv212m64i (rev 0.9) revision 0.9 - 2 - 2000/11/17 pin connection note: as long as the pin sequence is not changed, the pin-out of 42 pin sdip is negotiable according to customers ? demand. mtv212m64i 40 pin pdip da2/p5.2 40 1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 da1/p5.1 da0/p5.0 rst vdd vss x2 x1 isda/p3.4/t0 iscl/p3.5/t1 stout/p4.2 p2.2/ad2 p1.0 p1.1 p3.2/int0 p1.2 p1.3 p1.4 p1.5 p1.6 hsync da3/p5.3 vsync da4/p5.4 da8/halfh da9/halfv da5/p5.5 hblank/p4.1 da7/hclamp da6/p5.6 vblank/p4.0 p2.7/da13 p2.5/da11 p2.4/da10 p2.6/da12 hscl/p3.0/rxd p2.0/ad0 p2.1/ad1 hsda/p3.1/txd p1.7 mtv212m64i 42 pin sdip da2/p5.2 40 1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 da1/p5.1 da0/p5.0 rst vdd vss x2 x1 isda/p3.4/t0 iscl/p3.5/t1 stout/p4.2 p2.2/ad2 p1.0 p1.1 p3.2/int0 p1.2 p1.3 nc nc nc hsync da3/p5.3 vsync da4/p5.4 da8/halfh da9/halfv da5/p5.5 hblank/p4.1 da7/hclamp da6/p5.6 vblank/p4.0 p1.6 p2.4/da10 p1.5 hscl/p3.0/rxd p2.0/ad0 p2.1/ad1 hsda/p3.1/txd p1.7 42 41 p2.5/da11 p2.6/da12 p1.4 mtv212m64i 44 pin plcc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 p1.6 24 p1.7 p2.1/ad1 p1.5 p2.0/ad0 hsda/p3.1/txd p1.1 p3.2/int0 p1.2 p1.3 p1.4 23 22 21 20 28 27 26 25 nc 6 5 4 3 2 1 44 43 42 41 40 nc nc da0/p5.0 da1/p5.1 da2/p5.2 vsync hsync da3/p5.3 da4/p5.4 da5/p5.5 19 18 rst vdd vss x2 x1 isda/p3.4/t0 iscl/p3.5/t1 stout/p4.2 p2.2/ad2 p1.0 p2.3/ad3 p2.4/da10 hscl/p3.0/rxd p2.5/da11 p2.6/da12 da8/halfh da9/halfv hblank/p4.1 da7/hclamp da6/p5.6 vblank/p4.0 p2.7/da13
myson technology mtv212m64i (rev 0.9) revision 0.9 - 3 - 2000/11/17 pin description name type description da2/p5.2 i/o pwm dac output (5v open drain) / general purpose i/o (5v open drain) da1/p5.1 i/o pwm dac output (5v open drain) / general purpose i/o (5v open drain) da0/p5.0 i/o pwm dac output (5v open drain) / general purpose i/o (5v open drain) rst i active high reset vdd - positive power supply p2.3/ad3 i/o general purpose i/o (cmos output or 8051 standard) / adc input vss - ground x2 o oscillator output x1 i oscillator input isda/p3.4/t0 i/o master iic data (5v open drain) / general purpose i/o (8051 standard) / t0 iscl/p3.5/t1 i/o master iic clock (5v open drain) / general purpose i/o (8051 standard) / t1 stout/p4.2 o self-test video output (cmos) / general purpose output (cmos) p2.2/ad2 i/o general purpose i/o (cmos output or 8051 standard) / adc input p1.0 i/o general purpose i/o (cmos output or 8051 standard) p1.1 i/o general purpose i/o (cmos output or 8051 standard) p3.2/int0 i general purpose input / int0 p1.2 i/o general purpose i/o (cmos output or 8051 standard) p1.3 i/o general purpose i/o (cmos output or 8051 standard) p1.4 i/o general purpose i/o (cmos output or 8051 standard) p1.5 i/o general purpose i/o (cmos output or 8051 standard) p1.6 i/o general purpose i/o (cmos output or 8051 standard) p1.7 i/o general purpose i/o (cmos output or 8051 standard) p2.1/ad1 i/o general purpose i/o (cmos output or 8051 standard) / adc input p2.0/ad0 i/o general purpose i/o (cmos output or 8051 standard) / adc input hsda/p3.1/txd i/o slave iic data (5v open drain) / general purpose i/o (8051 standard) / txd hscl/p3.0/rxd i/o slave iic clock (5v open drain) / general purpose i/o (8051 standard) / rxd p2.4/da10 i/o general purpose i/o (cmos output or 8051 standard) / pwm dac output (cmos) p2.5/da11 i/o general purpose i/o (cmos output or 8051 standard) / pwm dac output (cmos) p2.6/da12 i/o general purpose i/o (cmos output or 8051 standard) / pwm dac output (cmos) p2.7/da13 i/o general purpose i/o (cmos output or 8051 standard) / pwm dac output (cmos) da6/p5.6 i/o pwm dac output (cmos) / general purpose i/o (cmos output or open drain i/o) da7/hclamp o pwm dac output (cmos) / hsync clamp pulse output (cmos) vblank/p4.0 o vertical blank (cmos) / general purpose output (cmos) hblank/p4.1 o horizontal blank (cmos) / general purpose output (cmos) da9/halfv o pwm dac output (5v open drain) / vsync half freq. output (5v open drain) da8/halfh o pwm dac output (5v open drain) / hsync half freq. output (5v open drain) da5/p5.5 i/o pwm dac output (cmos) / general purpose i/o (cmos output or open drain i/o) da4/p5.4 i/o pwm dac output (cmos) / general purpose i/o (cmos output or open drain i/o) da3/p5.3 i/o pwm dac output (cmos) / general purpose i/o (cmos output or open drain i/o) hsync i horizontal sync or composite sync input vsync i vertical sync input
myson technology mtv212m64i (rev 0.9) revision 0.9 - 4 - 2000/11/17 pin configuration a ? cmos output pin ? means it can sink and drive at least 4ma current. it ? s not recommended to use such pin as input function. a ? 5v open drain pin ? means it can sink at least 4ma current but only drive 10~20ua to vdd. it can be used as input or output function and needs an external pull up resistor. a ? 8051 standard pin ? is a pseudo open drain pin. it can sink at least 4ma current when output is at low level, and drive at least 4ma current for 160ns when output transits from low to high, then keeps driving at 100ua to maintain the pin at high level. it can be used as input or output function. it needs an external pull up resistor when driving heavy load devices. 8051 standard pin 4ma 4ma output data pin cmos output pin 5v open drain pin 2 osc period delay 4ma 10ua output data 120ua pin 4ma input data no current 4ma output data pin input data
myson technology mtv212m64i (rev 0.9) revision 0.9 - 5 - 2000/11/17 functional descriptions 1. 8051 cpu core mtv212m64i includes all 8051 functions with the following exceptions: 1.1 the external ram access is restricted to xfrs/auxram within the mtv212m64i. 1.2 port0, port3.3, port3.6 and port3.7 are not general-purpose i/o ports. they are dedicated to monitor special application. 1.3 int1 input pin is not provided, it is connected to special interrupt sources. 1.4 port2 is shared by special fu n ction pins. in addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051. note: all registers listed in this document reside in external ram area (xfr). for internal ram memory map, please refer to 8051 spec. 2. memory allocation 2.1 internal special function registers ( sfr) the sfr is a group of registers that are the same as standard 8051. 2.2 internal ram there are total 256 bytes internal ram in mtv212m64i, same as standard 8052. 2.3 external special function registers (xfr) the xfr is a group of registers allocated in the 8051 external ram area 00h - 7fh. most of the registers are used for monitor control or pwm dac. program can initialize ri value and use "movx" instruction to access these registers. 2.4 auxiliary ram (auxram) there are a total of 768 bytes auxiliary ram allocated in the 8051 external ram area 80h - ffh. the auxram is divided into six banks, selected by xbank register. program can initialize ri value and use "movx" instruction to access the auxram. 00h 7fh 80h ffh auxram accessible by indirect external ram addressing (xbank=0)(using movx a ,@ ri instruction) xfr accessible by indirect external ram addressing (using movx a ,@ ri instruction auxram accessible by indirect external ram addressing (xbank=5)(using movx a ,@ ri instruction) 00h 7fh 80h ffh internal ram accessible by indirect addressing only (using mov a ,@ri instruction) internal ram accessible by direct and indirect addressing sfr accessible by direct addressing ? .. xbank= 2,3,4,5
myson technology mtv212m64i (rev 0.9) revision 0.9 - 6 - 2000/11/17 3. chip configuration the chip configuration registers define the chip pins function, as well as the connection, configuration and frequency of the functional blocks. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 padmod 30h (w) da13e da12e da11e da10e ad3e ad2e ad1e ad0e padmod 31h (w) p56e p55e p54e p53e p52e p51e p50e padmod 32h (w) hiice iiice hlfve hlfhe hclpe p42e p41e p40e padmod 3ah (w) cop17 cop16 cop15 cop14 cop13 cop12 cop11 cop10 padmod 3bh (w) cop27 cop26 cop25 cop24 cop23 cop22 cop21 cop20 padmod 3ch (w) cop56 cop55 cop54 cop53 option 33h (w) pwmf div253 fclke iicpass enscl msel miicf1 miicf0 option 34h (w) slvabs1 slvabs0 xbank 35h (r/w) xbnk2 xbnk1 xbnk0 padmod (w ) : pad mode control registers. (all are "0" in chip reset) da13e = 1 ? pin ? p2.7/da13 ? is da13. = 0 ? pin ? p2.7/da13 ? is p2.7. da12e = 1 ? pin ? p2.6/da12 ? is da12. = 0 ? pin ? p2.6/da12 ? is p2.6. da11e = 1 ? pin ? p2.5/da11 ? is da11. = 0 ? pin ? p2.5/da11 ? is p2.5. da10e = 1 ? pin ? p2.4/da10 ? is da10. = 0 ? pin ? p2.4/da10 ? is p2.4. ad3e = 1 ? pin ? p2.3/ad3 ? is ad3. = 0 ? pin ? p2.3/ad3 ? is p2.3. ad2e = 1 ? pin ? p2.2/ad2 ? is ad2. = 0 ? pin ? p2.2/ad2 ? is p2.2. ad1e = 1 ? pin ? p2.1/ad1 ? is ad1. = 0 ? pin ? p2.1/ad1 ? is p2.1. ad0e = 1 ? pin ? p2.0/ad0 ? is ad0. = 0 ? pin ? p2.0/ad0 ? is p2.0. p56e = 1 ? pin ? da6/p5.6 ? is p5.6. = 0 ? pin ? da6/p5.6 ? is da6. p55e = 1 ? pin ? da5/p5.5 ? is p5.5. = 0 ? pin ? da5/p5.5 ? is da5. p54e = 1 ? pin ? da4/p5.4 ? is p5.4. = 0 ? pin ? da4/p5.4 ? is da4. p53e = 1 ? pin ? da3/p5.3 ? is p5.3. = 0 ? pin ? da3/p5.3 ? is da3. p52e = 1 ? pin ? da2/p5.2 ? is p5.2. = 0 ? pin ? da2/p5.2 ? is da2. p51e = 1 ? pin ? da1/p5.1 ? is p5.1. = 0 ? pin ? da1/p5.1 ? is da1. p50e = 1 ? pin ? da0/p5.0 ? is p5.0. = 0 ? pin ? da0/p5.0 ? is da0. hiice = 1 ? pin ? hscl/p3.0/rxd ? is hscl ; pin ? hsda/p3.1/txd ? is hsda. = 0 ? pin ? hscl/p3.0/rxd ? is p3.0/rxd; pin ? hsda/p3.1/txd ? is p3.1/txd. iiice = 1 ? pin ? isda/p3.4/t0 ? is isda; pin ? iscl/p3.5/t1 ? is iscl. = 0 ? pin ? isda/p3.4/t0 ? is p3.4/t0; pin ? iscl/p3.5/t1 ? is p3.5/t1. hlfve = 1 ? pin ? da9/halfv ? is vsync half frequency output.
myson technology mtv212m64i (rev 0.9) revision 0.9 - 7 - 2000/11/17 = 0 ? pin ? da9/halfv ? is da9. hlfhe = 1 ? pin ? da8/halfh ? is hsync half frequency output. = 0 ? pin ? da8/halfh ? is da8. hclpe = 1 ? pin ? da7/hclamp ? is hsync clamp pulse output. = 0 ? pin ? da7/hclamp ? is da7. p42e = 1 ? pin ? stout/p4.2 ? is p4.2. = 0 ? pin ? stout/p4.2 ? is stout. p41e = 1 ? pin ? hblank/p4.1 ? is p4.1. = 0 ? pin ? hblank/p4.1 ? is hblank. p40e = 1 ? pin ? vblank/p4.0 ? is p4.0. = 0 ? pin ? vblank/p4.0 ? is vblank. cop17 = 1 ? pin ? p1.7 ? is cmos output. = 0 ? pin ? p1.7 ? is 8051 standard i/o. cop16 = 1 ? pin ? p1.6 ? is cmos output. = 0 ? pin ? p1.6 ? is 8051 standard i/o. cop15 = 1 ? pin ? p1.5 ? is cmos output. = 0 ? pin ? p1.5 ? is 8051 standard i/o. cop14 = 1 ? pin ? p1.4 ? is cmos output. = 0 ? pin ? p1.4 ? is 8051 standard i/o. cop13 = 1 ? pin ? p1.3 ? is cmos output. = 0 ? pin ? p1.3 ? is 8051 standard i/o. cop12 = 1 ? pin ? p1.2 ? is cmos output. = 0 ? pin ? p1.2 ? is 8051 standard i/o. cop11 = 1 ? pin ? p1.1 ? is cmos output. = 0 ? pin ? p1.1 ? is 8051 standard i/o. cop10 = 1 ? pin ? p1.0 ? is cmos output. = 0 ? pin ? p1.0 ? is 8051 standard i/o. cop27 = 1 ? pin ? p2.7/da13 ? is cmos data output. = 0 ? pin ? p2.7/da13 ? is 8051 standard i/o or cmos pwm dac output. cop26 = 1 ? pin ? p2.6/da12 ? is cmos data output. = 0 ? pin ? p2.6/da12 ? is 8051 standard i/o or cmos pwm dac output. cop25 = 1 ? pin ? p2.5/da11 ? is cmos data output. = 0 ? pin ? p2.5/da11 ? is 8051 standard i/o or cmos pwm dac output. cop24 = 1 ? pin ? p2.4/da10 ? is cmos data output. = 0 ? pin ? p2.4/da10 ? is 8051 standard i/o or cmos pwm dac output. cop23 = 1 ? pin ? p2.3/ad3 ? is cmos data output. = 0 ? pin ? p2.3/ad3 ? is 8051 standard i/o or adc input. cop22 = 1 ? pin ? p2.2/ad2 ? is cmos data output. = 0 ? pin ? p2.2/ad2 ? is 8051 standard i/o or adc input. cop21 = 1 ? pin ? p2.1/ad1 ? is cmos data output. = 0 ? pin ? p2.1/ad1 ? is 8051 standard i/o or adc input. cop20 = 1 ? pin ? p2.0/ad0 ? is cmos data output. = 0 ? pin ? p2.0/ad0 ? is 8051 standard i/o or adc input. cop56 = 1 ? pin ? da6/p5.6 ? is cmos data output. = 0 ? pin ? da6/p5.6 ? is open drain i/o or cmos pwm dac. cop55 = 1 ? pin ? da5/p5.5 ? is cmos data output. = 0 ? pin ? da5/p5.5 ? is open drain i/o or cmos pwm dac. cop54 = 1 ? pin ? da4/p5.4 ? is cmos data output. = 0 ? pin ? da4/p5.4 ? is open drain i/o or cmos pwm dac. cop53 = 1 ? pin ? da3/p5.3 ? is cmos data output. = 0 ? pin ? da3/p5.3 ? is open drain i/o or cmos pwm dac.
myson technology mtv212m64i (rev 0.9) revision 0.9 - 8 - 2000/11/17 option (w ) : chip option configuration (all are "0" in chip reset) . pwmf = 1 ? selects 94khz pwm frequency. = 0 ? selects 47khz pwm frequency. div253 = 1 ? pwm pulse width is 253-step resolution. = 0 ? pwm pulse width is 256-step resolution. fclke = 1 ? double cpu clock freq. iicpass = 1 ? hscl/hsda pin bypasses to iscl/isda pin in ddc2 mode. = 0 ? separates master and slave iic block. enscl = 1 ? enables slave iic block to hold hscl pin low while mtv212m64i is unable to catch up the external master's speed. msel = 1 ? master iic block connects to hscl/hsda pins. = 0 ? master iic block connects to iscl/isda pins. miicf1 ,miicf0 = 1,1 ? selects 400khz master iic frequency. = 1,0 ? selects 200khz master iic frequency. = 0,1 ? selects 50khz master iic frequency. = 0,0 ? selects 100khz master iic frequency. slvabs1 ,slvabs0 : slave address length of slave iic block a. = 1,0 ? 5-bits slave address. = 0,1 ? 6-bits slave address. = 0,0 ? 7-bits slave address. xbank (r/w ) : auxiliary ram bank switch. xbnk [2:0] = 0 ? selects auxram bank 0. = 1 ? selects auxram bank 1. = 2 ? selects auxram bank 0. = 3 ? selects auxram bank 1. = 4 ? selects auxram bank 0. = 5 ? selects auxram bank 1. 4. extra i/o the extra i/o is a group of i/o pins located in xfr area. port4 is output mode only. port5 can be used as both output and input for that the pin of port5 is open drain type, users must write corresponding bit of port5 to "1" in input mode. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 port4 38h (w) p42 p41 p40 port5 39h (r/w) p56 p55 p54 p53 p52 p51 p50 port4 (w ) : port 4 data output value. port5 (r/w ) : port 5 data input/output value. 5. pwm dac each output pulse width of pwm dac converter is controlled by an 8-bit register in xfr. the frequency of pwm clk is 47khz or 94khz, selected by pwmf. and the total duty cycle step of these dac outputs is 253 or 256, selected by div253. if div253=1, writing fdh/feh/ffh to dac register generates stable high output. if div253=0, the output will pulse low at least once even if the content of dac register is ffh. writing 00h to dac register generates stable low output.
myson technology mtv212m64i (rev 0.9) revision 0.9 - 9 - 2000/11/17 reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 da0 20h (r/w) pulse width of pwm dac 0 da1 21h (r/w) pulse width of pwm dac 1 da2 22h (r/w) pulse width of pwm dac 2 da3 23h (r/w) pulse width of pwm dac 3 da4 24h (r/w) pulse width of pwm dac 4 da5 25h (r/w) pulse width of pwm dac 5 da6 26h (r/w) pulse width of pwm dac 6 da7 27h (r/w) pulse width of pwm dac 7 da8 28h (r/w) pulse width of pwm dac 8 da9 29h (r/w) pulse width of pwm dac 9 da10 2ah (r/w) pulse width of pwm dac 10 da11 2bh (r/w) pulse width of pwm dac 11 da12 2ch (r/w) pulse width of pwm dac 12 da13 2dh (r/w) pulse width of pwm dac 13 da0-13 (r/w ) : the output pulse width control for da0-13. * all of pwm dac converters are centered with value 80h after power on. 6. h/v sync processing the h/v sync processing block performs the functions of composite signal separation/insertion. sync inputs presence check, frequency counting, polarity detection and control, as well as the protection of vblank output while vsync speeds up in high ddc communication clock rate. the present and frequency function block treat any pulse shorter than one osc period as noise. hself hpol cvpre vbpl vsync digital filter polarity check & sync seperator vpre present check vfreq vpol polarity check & freq. count xor vblank vself xor hsync digital filter cvsync present check hpre hfreq present check & freq. count hbpl xor hblank xor composite pulse insert h/v sync processor block diagram
myson technology mtv212m64i (rev 0.9) revision 0.9 - 10 - 2000/11/17 6.1 composite sync separation/insertion the mtv212m64i continuously monitors the input hsync, if the vertical sync pulse can be extracted from the input, a cvpre flag is set and users can select the extracted "cvsync" for the source of polarity check, frequency count, and vblank output. the cvsync will have 8us delay compared to the original signal. the mtv212m64i can also insert pulse to hblank output during composite active time of vsync. the insert pulse ? s width is 1/8 hsync period and the insertion frequency can adapt to original hsync. the hblank pulse can be disabled or enabled by setting ? nohins ? control bit. 6.2 h/v frequency counter mtv212m64i can discriminate hsync/vsync frequency and save the information in xfrs. the 14 bits hcounter counts the time of 64xhsync period, then loads the result into the hcnth/hcntl latch. the output value will be [(128000000/h-freq) - 1], updated once per vsync/cvsync period when vsync/cvsync is present or continuously updated when vsync/cvsync is non-present. the 12 bits vcounter counts the time between two vsync pulses, then loads the result into the vcnth/vcntl latch. the output value will be (62500/v-freq), updated every vsync/cvsync period. an extra overflow bit indicates the condition of h/v counter overflow. the vfchg/ hfchg interrupt is set when vcnt/hcnt value changes or overflows. table 4.2.1 and table 4.2.2 show the hcnt/vcnt value under the operations of 12mhz. 6.2.1 h- freq table output value (14 bits) h- freq( khz) 12mhz osc (hex / dec) 1 31.5 0fdeh / 4062 2 37.5 0d54h / 3412 3 43.3 0b8bh / 2955 4 46.9 0aa8h / 2728 5 53.7 094fh / 2383 6 60.0 0854h / 2132 7 68.7 0746h / 1862 8 75.0 06aah / 1706 9 80.0 063fh / 1599 10 85.9 05d1h / 1489 11 93.8 0554h / 1364 12 106.3 04b3h / 1203 6.2.2 v- freq table output value (12bits) v- freq(hz) 12mhz osc (hex / dec) 1 56 45ch / 1116 2 60 411h / 1041 3 70 37ch / 892 4 72 364h / 868 5 75 341h / 833 6 85 2dfh / 735 6.3 h/v present check the hpresent function checks the input hsync pulse, hpre flag is set when hsync is over 10khz or cleared when hsync is under 10hz. the vpresent function checks the input vsync pulse, the vpre flag is set when vsync is over 40hz or cleared when vsync is under 10hz. the hprchg interrupt is set when the hpre value changes. the vprchg interrupt is set when the vpre/ cvpre value change. however, the cvpre flag interrupt may be disabled when s/w disables the composite function.
myson technology mtv212m64i (rev 0.9) revision 0.9 - 11 - 2000/11/17 6.4 h/v polarity detect the polarity functions detect the input hsync/vsync high and low pulse duty cycle. if the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. the hplchg interrupt is set when the hpol value changes. the vplchg interrupt is set when the vpol value changes. 6.5 output hblank/vblank control and polarity adjust the hblank is the mux output of hsync, composite hpulse and self-test horizontal pattern. the vblank is the mux output of vsync, cvsync and self-test vertical pattern. the mux selection and output polarity are s/w controllable. the vblank output is cut off when vsync frequency is over 200hz. the hblank/vblank shares the output pin with p4.1/ p4.0. 6.6 self-test pattern generator for testing purposes, this generator can generate 4 display patterns, which are positive cross-hatch, negative cross-hatch, full white, and full black (showed as following figure). the hblank output frequency of the pattern can be chosen to 95.2khz, 63.5khz, 47.6khz and 31.75khz. the vblank output frequency of the pattern is 72hz or 60hz. it is originally designed to support monitor manufacturers to do burn-in test, or offer end-users a reference to check the monitor. the output stout of the generator shares the output pin with p4.2. display region positive cross-hatch negative cross-hatch full white full black
myson technology mtv212m64i (rev 0.9) revision 0.9 - 12 - 2000/11/17 mtv212m64i self-test pattern timing 63.5khz, 60hz 47.6khz, 60hz 31.7khz, 60hz 95.2khz, 72hz time h dots time h dots time h dots time h dots hor. total time (a) 15.75us 1280 21.0us 1024 31.5us 640 10.5us 1600 hor. active time (d) 12.05us 979.3 16.07us 783.2 24.05us 488.6 8.03us 1224 hor. f. p. (e) 0.2us 16.25 0.28us 12 0.45us 9 0.14us 21 sync pulse width (b) 1.5us 122 2us 90 3us 61 1.0us 152 hor. b. p. (c) 2us 162.54 2.67us 110 4us 81.27 1.33us 203 time v lines time v lines time v lines time v lines vert. total time (o) 16.66ms 1024 16.66ms 768 16.66ms 480 13.89ms 1200 vert. active time (r) 15.65ms 962 15.65ms 721.5 15.65ms 451 13.03ms 1126 vert. f. p. (s) 0.063ms 3.87 0.063ms 2.9 0.063ms 1.82 0.052ms 4.5 sync pulse width (p) 0.063ms 3.87 0.063ms 2.9 0.063ms 1.82 0.052ms 4.5 vert. b. p. (q) 0.882ms 54.2 0.882ms 40.5 0.882ms 25.4 0.756ms 65 * 8 x 8 blocks of cross hatch pattern in display region. 6.7 hsync clamp pulse output the hclamp output is active by setting ? hclpe ? control bit. the leading edge position, pulse width and polarity of hclamp are s/w controllable. 6.8 vsync interrupt the mtv212m64i checks the vsync input pulse and generates an interrupt at its leading edge. the vsync flag is set each time when mtv212m64i detects a vsync pulse. the flag is cleared by s/w writing a "0".
myson technology mtv212m64i (rev 0.9) revision 0.9 - 13 - 2000/11/17 6.9 h/v sync processor register reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hvstus 40h (r) cvpre hpol vpol hpre vpre hoff voff hcnth 41h (r) hovf hf13 hf12 hf11 hf10 hf9 hf8 hcntl 42h (r) hf7 hf6 hf5 hf4 hf3 hf2 hf1 hf0 vcnth 43h (r) vovf vf11 vf10 vf9 vf8 vcntl 44h (r) vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 hvctr0 40h (w) c1 c0 nohins selexh ivhlfh hlfhe hbpl vbpl hvctr2 42h (w) selft stf1 stf0 rt1 rt0 ste hvctr3 43h (w) clpeg clppo clpw2 clpw1 clpw0 intflg 48h (r/w) hprchg vprchg hplchg vplchg hfchg vfchg vsync inten 49h (w) ehpr evpr ehpl evpl ehf evf evsync hvstus (r ) : the status of polarity, present and static level for hsync and vsync. cvpre = 1 ? the extracted cvsync is present. = 0 ? the extracted cvsync is not present. h pol = 1 ? hsync input is positive polarity. = 0 ? hsync input is negative polarity. v pol = 1 ? vsync (cvsync) is positive polarity. = 0 ? vsync (cvsync) is negative polarity. h pre = 1 ? hsync input is present. = 0 ? hsync input is not present. v pre = 1 ? vsync input is present. = 0 ? vsync input is not present. h off* = 1 ? off level of hsync input is high. = 0 ? off level of hsync input is low. v off* = 1 ? off level of vsync input is high. = 0 ? off level of vsync input is low. *h off and v off are valid when h pre=0 or v pre=0. hcnth (r ) : h- freq counter's high bits. hovf = 1 ? h- freq counter is overflowed, this bit is cleared by h/w when condition removed. hf13 - hf8 : 6 high bits of h- freq counter. hcntl (r ) : h- freq counter's low byte. vcnth (r ) : v- freq counter's high bits. vovf = 1 ? v- freq counter is overflowed, this bit is cleared by h/w when condition removed. vf11 - 8 : 4 high bits of v- freq counter. vcntl (r ) : v- freq counter's low byte. hvctr0 (w ) : h/v sync processor control register 0. c1, c0 = 1,1 ? selects cvsync as the polarity, freq and vblank source. = 1,0 ? selects vsync as the polarity, freq and vblank source. = 0,0 ? disables composite function. = 0,1 ? h/w automatically switches to cvsync when cvpre=1 and vspre=0. nohins = 1 ? hblank has no insert pulse in composite mode. = 0 ? hblank has insert pulse in composite mode. selexh = 1 ? input source of hlfho is p1.0. = 0 ? input source hlfho is hsync.
myson technology mtv212m64i (rev 0.9) revision 0.9 - 14 - 2000/11/17 ivhlfh = 1 ? hlfho is inverted. = 0 ? hlfho is not inverted. hlfhe = 1 ? hlfho is half freq. of hsync/p1.0. = 0 ? hlfho is same freq. of hsync/p1.0. hb pl = 1 ? negative polarity hblank output. = 0 ? positive polarity hblank output. vb pl = 1 ? negative polarity vblank output. = 0 ? positive polarity vblank output. hvctr2 (w ) : self-test pattern generator control. s elft = 1 ? enables generator. = 0 ? disables generator. stf1 ,stf0 = 1,1 ? 95.2khz(horizontal)/72hz(vertical) output selected. = 1,0 ? 63.5khz(horizontal)/60hz(vertical) output selected. = 0,1 ? 47.6khz(horizontal) /60hz(vertical) output selected. = 0,0 ? 31.75khz(horizontal) /60hz(vertical) output selected. rt1 ,rt0 = 0,0 ? positive cross-hatch pattern output. = 0,1 ? negative cross-hatch pattern output. = 1,0 ? full white pattern output. = 1,1 ? full black pattern output. ste = 1 ? enables stout output. = 0 ? disables stout output. hvctr3 (w ) : hsync clamp pulse control register. clpeg = 1 ? clamp pulse follows hsync leading edge. = 0 ? clamp pulse follows hsync trailing edge. clppo = 1 ? positive polarity clamp pulse output. = 0 ? negative polarity clamp pulse output. clpw2 : clpw0 : pulse width of clamp pulse is [(clpw2 :clpw0) + 1] x 0.167 m s for 12mhz x ? tal selection. intflg (w ) : interrupt flag . an interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the int1 source of 8051 core will be driven by a zero level. software must clear this register while serving the interrupt routine. hprchg= 1 ? no action. = 0 ? clears hsync presence change flag. vprchg= 1 ? no action. = 0 ? clears vsync presence change flag. hplchg = 1 ? no action. = 0 ? clears hsync polarity change flag. vplchg = 1 ? no action. = 0 ? clears vsync polarity change flag. hfchg = 1 ? no action. = 0 ? clears hsync frequency change flag. vfchg = 1 ? no action. = 0 ? clears vsync frequency change flag. vsync = 1 ? no action. = 0 ? clears vsync interrupt flag. intflg (r ) : interrupt flag. hprchg= 1 ? indicates a hsync presence change. vprchg= 1 ? indicates a vsync presence change. hplchg = 1 ? indicates a hsync polarity change.
myson technology mtv212m64i (rev 0.9) revision 0.9 - 15 - 2000/11/17 vplchg = 1 ? indicates a vsync polarity change. hfchg = 1 ? indicates a hsync frequency change or counter overflow. vfchg = 1 ? indicates a vsync frequency change or counter overflow. vsync = 1 ? indicates a vsync interrupt. inten (w ) : interrupt enable. ehpr = 1 ? enables hsync presence change interrupt. evpr = 1 ? enables vsync presence change interrupt. ehpl = 1 ? enables hsync polarity change interrupt. evpl = 1 ? enables vsync polarity change interrupt. ehf = 1 ? enables hsync frequency change / counter overflow interrupt. evf = 1 ? enables vsync frequency change / counter overflow interrupt. evsync = 1 ? enables vsync interrupt. 7. ddc & iic interface 7.1 ddc1 mode the mtv212m64i enters ddc1 mode after reset. in this mode, vsync is used as data clock. the hscl pin should remain at high. the data output to the hsda pin is taken from a shift register in mtv212m64i. the shift register fetches data byte from the ddc1 data buffer (dbuf) then sends it in 9 bits packet formats which includes a null bit (=1) as packet separator. the dbuf sets the dbufi interrupt flag when the shift register reads out the data byte from dbuf. software needs to write edid data to dbuf as soon as the dbufi is set. the dbufi interrupt is automatically cleared when software writes a new data byte to dbuf. the dbufi interrupt can be masked or enabled by edbufi control bit. 7.2 ddc2b mode the mtv212m64i switches to ddc2b mode when it detects a high to low transition on the hscl pin. once mtv212m64i enters ddc2b mode, s/w can set iicpass control bit to allow host accessing eeprom directly. under such condition, the hsda and hscl are directly bypassed to isda and iscl pins. the other way to perform ddc2 function is to clear iicpass and config the slave a iic block to act as eeprom behavior. the slave address of slave a block can be chosen by s/w as 5-bits, 6-bits or 7-bits. for example, if s/w chooses 5-bits slave address as 10100b, the slave iic block a will respond to slave address 10100xxb and save the 2 lsb " xx" in xfr. this feature enables mtv212m64i to meet pc99 requirement. the mtv212m64i will return to ddc1 mode if hscl is kept high for 128 vsync clock period. however, it will lock in ddc2b mode if a valid iic address (1010xxxb) has been detected on hscl/hsda bus. the ddc2 flag reflects the current ddc status, s/w may clear it by writing a "0" to it. 7.3 slave mode iic function block the slave mode iic block is connected to hsda and hscl pins. this block can receive/transmit data using iic protocol. there are 2 slave addresses to which mtv212m64i can respond. s/w may write the slvaadr/slvbadr register to determine the slave addresses. the slave a address can be configured to 5-bits, 6-bits or 7-bits by s/w setting the slvabs1 and slvabs0 control bits. in receive mode, the block first detects iic slave address matching the condition, then issues a slvami/ slvbmi interrupt. if the matched address is slave a, mtv212m64i will save 2 lsb bits of the matched address to slvalsb1 and slvalsb0 register. the data from hsda is shifted into shift register then written to rcabuf/rcbbuf register when a data byte is received. the first byte loaded is word address (slave address is dropped). this block also generates a rcai/rcbi (receive buffer full interrupt) every time when the rcabuf/rcbbuf is loaded. if s/w is not able to read out the rcabuf/rcbbuf in time, the next byte in shift register will not be written to rcabuf/rcbbuf and the slave block returns nack to the master. this feature guarantees the data integrity of communication. the wadra/ wadrb flag can tell s/w whether the data in rcabuf/rcbbuf is a word address. in transmit mode, the block first detects iic slave address matching the condition, then issues a slvami/ slvbmi interrupt. in the mean time, the slvalsb1/slvalsb0 is also updated if the matched address is slave a, and the data pre-stored in the txabuf/txbbuf is loaded into shift register, resulting in
myson technology mtv212m64i (rev 0.9) revision 0.9 - 16 - 2000/11/17 txabuf/txbbuf emptying and generates a txai/txbi (transmits buffer empty interrupt). s/w should write the txabuf/txbbuf a new byte for the next transfer before shift register empties. a failure of this process will cause data corrupt. the txai/txbi occurs every time when shift register reads out the data from txabuf/txbbuf. the slvami/ slvbmi is cleared by writing "0" to corresponding bit in intflg register. the rcai/rcbi is cleared by reading rcabuf/rcbbuf. the txai/txbi is cleared by writing txabuf/txbbuf. if the control bit enscl is set, the block will hold hscl low until the rcai/rcbi/txai/txbi is cleared. *please see the attachments about "slave iic block timing". 7.4 master mode iic function block the master mode iic block can be connected to the isda /iscl pins or the hsda/hscl pins, selected by msel control bit. its speed can be selected to 50khz-400khz by s/w setting the miicf1/miicf0 control bit. the software program can access the external iic device through this interface. since the edid/vdif data and the display information share the common eeprom, precaution must be taken to avoid bus conflicting while msel=0. in ddc1 mode or iicpass=0, the iscl/isda is controlled by mtv212m64i only. in ddc2 mode and iicpass flag is set, the host may access the eeprom directly. software can test the hscl condition by reading the hbusy flag, which is set in case of hscl=0, and keeps high for 100us after the hscl's rising edge. s/w can launch the master iic transmit/receive by clearing the p bit. once p=0, mtv212m64i will hold hscl low to isolate the access to eeprom of the host. a summary of master iic access is illustrated as follows. 7.4.1. to write iic device 1. write mbuf the slave address. 2. set s bit to start. 3. after the mtv212m64i transmit this byte, a mbufi interrupt will be triggered. 4. program can write mbuf to transfer next byte or set p bit to stop. * please see the attachments about "master iic transmit timing". 7.4.2. to read iic device 1. write mbuf the slave address. 2. set s bit to start. 3. after the mtv212m64i transmit this byte, a mbufi interrupt will be triggered. 4. set or reset the macko flag according to the iic protocol. 5. read out mbuf the useless byte to continue the data transfer. 6. after the mtv212m64i receives a new byte, the mbufi interrupt is triggered again. 7. read mbuf also trigger the next receive operation, but set p bit before read can terminate the operation. * please see the attachments about "master iic receive timing". reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iicctr 00h (r/w) ddc2 macko p s iicstus 01h (r) wadrb wadra slvrwb sackin slvs slvalsb1 slvalsb0 iicstus 02h (r) mackin hifreq hbusy intflg 03h (r) txbi rcbi slvbmi txai rcai slvami dbufi mbufi intflg 03h (w) slvbmi slvami mbufi inten 04h (w) etxbi ercbi eslvbmi etxai ercai eslvami edbufi embufi mbuf 05h (r/w) master iic receive/transmit data buffer rcabuf 06h (r) slave a iic receive buffer txabuf 06h (w) slave a iic transmit buffer slvaadr 07h (w) enslva slave a iic address rcbbuf 08h (r) slave b iic receive buffer txbbuf 08h (w) slave b iic transmit buffer slvbadr 09h (w) enslvb slave b iic address dbuf 0ah (w) ddc1 transmit data buffer
myson technology mtv212m64i (rev 0.9) revision 0.9 - 17 - 2000/11/17 iicctr (r/w ) : iic interface control register. ddc2 = 1 ? mtv212m64i is in ddc2 mode, write "0" can clear it. = 0 ? mtv212m64i is in ddc1 mode. macko = 1 ? in master receive mode, nack is returned by mtv212m64i. = 0 ? in master receive mode, ack is returned by mtv212m64i. s, p = - , 0 ? start condition when master iic is not during transfer. = x, - ? stop condition when master iic is not during transfer. = 1, x ? will resume transfer after a read/write mbuf operation. = x, 0 ? force hscl low and occupy the master iic bus. * a write/read mbuf operation can be recognized only after 10us of the mbufi flag's rising edge. iicstus (r ) : iic interface status register. wadrb = 1 ? the data in rcbbuf is word address. wadra = 1 ? the data in rcabuf is word address. slv rwb = 1 ? current transfer is slave transmit = 0 ? current transfer is slave receive sackin = 1 ? the external iic host respond nack. slvs = 1 ? the slave block has detected a start, cleared when stop detected. slvalsb1 ,slvalsb0 : the 2 lsb which host sends to slave a block. mackin = 1 ? master iic bus error, no ack received from the slave iic device. = 0 ? ack received from the slave iic device. hifreq = 1 ? mtv212m64i has detected a higher than 200hz clock on the vsync pin. hbusy = 1 ? host drives the hscl pin to low. intflg (w ) : interrupt flag. a int errupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 int1 source will be driven by a zero level. software must clear this register while serving the interrupt routine. slvbmi = 1 ? no action. = 0 ? clears slvbmi flag. slvami = 1 ? no action. = 0 ? clears slvami flag. mbufi = 1 ? no action. = 0 ? clears master iic bus interrupt flag ( mbufi). intflg (r ) : interrupt flag. txbi = 1 ? indicates the txbbuf needs a new data byte, cleared by writing txbbuf. rcbi = 1 ? indicates the rcbbuf has received a new data byte, cleared by reading rcbbuf. slvbmi = 1 ? indicates the slave iic address b matches condition. txai = 1 ? indicates the txabuf needs a new data byte, cleared by writing txabuf. rcai = 1 ? indicates the rcabuf has received a new data byte, cleared by reading rcabuf. slvami = 1 ? indicates the slave iic address a matches condition. dbufi = 1 ? indicates the ddc1 data buffer needs a new data byte, cleared by writing dbuf. mbufi = 1 ? indicates a byte is sent/received to/from the master iic bus. inten (w ) : interrupt enable. etxbi = 1 ? enables txbbuf interrupt. ercbi = 1 ? enables rcbbuf interrupt. eslvbmi = 1 ? enables slave address b match interrupt. etxai = 1 ? enables txabuf interrupt. ercai = 1 ? enables rcabuf interrupt. eslvami = 1 ? enables slave address a match interrupt.
myson technology mtv212m64i (rev 0.9) revision 0.9 - 18 - 2000/11/17 edbufi = 1 ? enables ddc1 data buffer interrupt. embufi = 1 ? enables master iic bus interrupt. mbuf (w ) : master iic data shift register, after st art and before stop condition, writing this register will resume transmission of mtv212m64i to the iic bus. mbuf (r ) : master iic data shift register, after start and before stop condition, reading this register will resume receiving of mtv212m64i from the iic bus. rcabuf (r ) : slave iic block a receives data buffer. txabuf (w ) : slave iic block a transmits data buffer. slvaadr (w ) : slave iic block a's enable and address. enslva = 1 ? enables slave iic block a. = 0 ? disables slave iic block a. bit6-0 : slave iic address a to which the slave block should respond. rcbbuf (r ) : slave iic block b receives data buffer. txbbuf (w ) : slave iic block b transmits data buffer. slvbadr (w ) : slave iic block b's enable and address. enslvb = 1 ? enables slave iic block b. = 0 ? disables slave iic block b. bit6-0 : slave iic address b to which the slave block should respond. 8. low power reset (lvr) & watchdog timer when the voltage level of power supply is below 4.0v(+/-0.2v) for a specific period of time, the lvr will generate a chip reset signal. after the power supply is above 4.0v(+/-0.2v), lvr maintains in reset state for 144 xtal cycle to guarantee the chip exit reset condition with a stable x'tal oscillation. the watchdog timer automatically generates a device reset when it is overflowed. the interval of overflow is 0.25 sec x n, where n is a number from 1 to 8, and can be programmed via register wdt(2:0). the timer function is disabled after power on reset, users can activate this function by setting wen, and clear the timer by set wclr. 9. a/d converter the mtv212m64i is equipped with three 6-bit a/d converters , s/w can select the current convert channel by setting the sadc1/sadc0 bit. the refresh rate for the adc is osc freq./12288. the adc compare the input pin voltage with internal vdd*n/64 voltage (where n = 0 - 63). the adc output value is n when pin voltage is greater than vdd*n/64 and smaller than vdd*(n+1)/64. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adc 10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc 10h (r) adc convert result wdt 18h (w) wen wclr wdt2 wdt1 wdt0 wdt (w ) : watchdog timer control register. wen = 1 ? enables watchdog timer. wclr = 1 ? clears watchdog timer. wdt2: wdt0 = 0 ? overflow interval = 8 x 0.25 sec.
myson technology mtv212m64i (rev 0.9) revision 0.9 - 19 - 2000/11/17 = 1 ? overflow interval = 1 x 0.25 sec. = 2 ? overflow interval = 2 x 0.25 sec. = 3 ? overflow interval = 3 x 0.25 sec. = 4 ? overflow interval = 4 x 0.25 sec. = 5 ? overflow interval = 5 x 0.25 sec. = 6 ? overflow interval = 6 x 0.25 sec. = 7 ? overflow interval = 7 x 0.25 sec. adc (w ) : adc control. enadc = 1 ? enables adc. sadc0 = 1 ? selects adc0 pin input. sadc1 = 1 ? selects adc1 pin input. sadc2 = 1 ? selects adc2 pin input. sadc3 = 1 ? no action. adc (r ) : adc convert result. 10. in system programming function (isp) the flash memory can be programmed by a specific writer in parallel mode, or by iic host in serial mode while the system is working. the feature of isp is outlined as below: 1. single 5v power supply for program/erase/verify. 2. block erase: 128 byte at 4ms 3. whole flash erase (blank): 4ms 4. byte programming cycle time: 60us 5. read access time: 40ns 6. only one two-pin iic bus (shared with ddc2) is needed for isp in user/factory mode. 7. iic bus clock rates up to 140khz. 8. whole 32k byte flash programming within 3 sec. 9. crc check provides 100% coverage for all single/double bit errors. after power on/reset, the mtv212m64i is running the original rom code. once the s/w detects a isp request (by key or iic), s/w can accept the request following the steps below: 1. clear watchdog to prevent reset during isp period. 2. disable all interrupt to prevent cpu wake-up. 3. write iic address of isp slave to ispslv for communication. 4. write 93h to isp enable register (ispen) to enable isp. 5. enter 8051 idle mode. when isp is enabled, the mtv212m64i will disable watchdog reset and switch the flash interface to isp host in 15-22.5us. so s/w must enter idle mode immediately after enabling isp. in the 8051 idle mode, pwm dacs and i/o pins keep running at its former status. there are 4 types of iic bus transfer protocols in isp mode. command write s-tttttt10k-cccccccck-aaaaaaaak-p command read s-tttttt11k-cccccccck-aaaaaaaak-aaaaaaaak-rrrrrrrrk-rrrrrrrrk-p data write s-ttt ttt00k-aaaaaaaak-ddddddddk- ... ? ddddddddk-p data read s-tttttt00k-aaaaaaaak -(p)-s-tttttt01k-ddddddddk- ... ? ddddddddk-p
myson technology mtv212m64i (rev 0.9) revision 0.9 - 20 - 2000/11/17 , where s = start or re-start p = stop k = ack by host (0 or 1) k = ack by slave tttttt = isp slave address cccccccc = command x = don ? t care x = not defined aaaaaaaa = flash_ address [15:8] aaaaaaaa = flash_address[7:0] rrrrrrrr = crc_ register [15:8] rrrrrrrr = crc_register[7:0] dddddddd = flash_data cccccccc = 10100xxx ? program cccccccc = 00110xxx ? page erase 128 bytes (erase) cccccccc = 01101xxx ? erase entire flash (blank) cccccccc = 11010xxx ? clear crc_register ( clr_crc) cccccccc = 01001xxx ? reset mtv212m64i ( reset_cpu) 10.1 isp command write the 2nd byte of ? command write ? can define the operating mode of mtv212m64i in its ? data write ? stage , clear crc register, or reset mtv212m64i. the 3rd byte of command write defines the page address (a15-8) of flash memory. a command write may consist of 1,2 or 3 bytes. 10.2 isp command read the 2 nd byte echoes the current command in isp slave. the 3 rd and 4 th byte reflect the current flash address. the 5 th and 6 th byte report the crc result. a command read may consist of 2,3,4,5 or 6 bytes. 10.3 isp data write the 2 nd byte defines the low address (a7-0) of flash. after receiving the 3 rd byte, the mtv212m64i will execute a program/erase/blank command depending on the preceding ? command write ? . the low address of flash will increase every time when isp slave acknowledges the data byte. the blank/erase command needs one data byte (content is ? don ? t care ? ). the executing time is 4ms. during the 4ms period, the isp slave does not accept any command/data and returns non- ack to any iic bus activity. the program command may have 1-256 data bytes. the program cycle time is 60us. if the isp slave is unable to complete the program cycle in time, it will return non- ack to the following data byte. in the meantime, the low address does not increase and the crc does not count the non- acked data byte. a data write may consist of 1,2 or more bytes. data write (blank/erase) s-tttttt00k-aaaaaaaak-ddddddddk-p ... s- ttttttxxk- |-----min. 4ms----| data write (program) s-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ... |min. 60us| 10.4 isp data read the 1 st and 2 nd byte are the same as ? data write ? to define the low address of flash. between the 2 nd and 3 rd byte, the isp host may issue stop-start or only re-start. from the 4 th byte, the isp slave sends the data byte of flash to isp host. the low address automatically increases every time when data byte is transferred. 10.5 cyclic redundancy check (crc) to shorten the verify time, the isp slave providse a simple way to check whether data error occurs during the program data transfer. after the isp host sends a lot of data bytes to isp slave, host can use command read to check result of crc register instead of reading every byte in flash. the crc register counts every data byte which isp slave acknowledges during ? data write ? period. however, the low address byte and the data byte of erase/blank are not counted. the clear crc command will write all ? 1 ? to the 16-bit crc register. for crc generation, the 16-bit crc register is seeded with all ? 1 ? pattern (by device reset or clear crc command). the data byte shifted into the crc register is msb first. the real implementation is described as follows:
myson technology mtv212m64i (rev 0.9) revision 0.9 - 21 - 2000/11/17 crcin = crc[15]^ datain; crc[15:0] = {crc[14]^ crcin, crc[13:2], crc[1]^ crcin, crc[0], crcin}; where ^ = xor example: data _byte crc_register_remainder ffffh f6h ff36h 28h 34f2h c3h 7031h 10.6 reset device after the flash has completed programming and verified ok, the isp host can use ? command write ? with reset_cpu command to wake up mtv212m64i . reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ispslv 0bh (w) isp slave address ispen 0ch (w) write 93h to enable isp mode test mode condition in normal application, users should avoid the mtv212m64i entering its test mode or writer mode, outlined as follows, adding pull-up resistor to da8 and da9 pins is recommended. test mode a: reset=1 & da9=1 & da8=0 & sto=0 test mode b: reset's falling edge & da9=1 & da8=0 & sto=1 writer mode: reset=1 & da9=0 & da8=1 memory map of xfr reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iicctr 00h (r/w) ddc2 macko p s iicstus 01h (r) wadrb wadra slvrwb sackin slvs slvalsb1 slvalsb0 iicstus 02h (r) mackin hifreq hbusy intflg 03h (r) txbi rcbi slvbmi txai rcai slvami dbufi mbufi intflg 03h (w) slvbmi slvami mbufi inten 04h (w) etxbi ercbi eslvbmi etxai ercai eslvami edbufi embufi mbuf 05h (r/w) master iic receives/transmits data buffer rcabuf 06h (r) slave a iic receives buffer txabuf 06h (w) slave a iic transmits buffer slvaadr 07h (w) enslva slave a iic address rcbbuf 08h (r) slave b iic receives buffer txbbuf 08h (w) slave b iic transmits buffer slvbadr 09h (w) enslvb slave b iic address dbuf 0ah (w) ddc1 transmits data buffer ispslv 0bh (w) isp slave address ispen 0ch (w) write 93h to enable isp mode adc 10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc 10h (r) adc convert result wdt 18h (w) wen wclr wdt2 wdt1 wdt0 da0 20h (r/w) pulse width of pwm dac 0 da1 21h (r/w) pulse width of pwm dac 1
myson technology mtv212m64i (rev 0.9) revision 0.9 - 22 - 2000/11/17 da2 22h (r/w) pulse width of pwm dac 2 da3 23h (r/w) pulse width of pwm dac 3 da4 24h (r/w) pulse width of pwm dac 4 da5 25h (r/w) pulse width of pwm dac 5 da6 26h (r/w) pulse width of pwm dac 6 da7 27h (r/w) pulse width of pwm dac 7 da8 28h (r/w) pulse width of pwm dac 8 da9 29h (r/w) pulse width of pwm dac 9 da10 2ah (r/w) pulse width of pwm dac 10 da11 2bh (r/w) pulse width of pwm dac 11 da12 2ch (r/w) pulse width of pwm dac 12 da13 2dh (r/w) pulse width of pwm dac 13 padmod 30h (w) da13e da12e da11e da10e ad3e ad2e ad1e ad0e padmod 31h (w) p56e p55e p54e p53e p52e p51e p50e padmod 32h (w) hiice iiice hlfve hlfhe hclpe p42e p41e p40e option 33h (w) pwmf div253 fclke iicpass enscl msel miicf1 miicf0 option 34h (w) slvabs1 slvabs0 xbank 35h (r/w) xbnk2 xbnk1 xbnk0 port4 38h (w) p42 p41 p40 port5 39h (r/w) p56 p55 p54 p53 p52 p51 p50 padmod 3ah (w) cop17 cop16 cop15 cop14 cop13 cop12 cop11 cop10 padmod 3bh (w) cop27 cop26 cop25 cop24 cop23 cop22 cop21 cop20 padmod 3ch (w) cop56 cop55 cop54 cop53 hvstus 40h (r) cvpre hpol vpol hpre vpre hoff voff hcnth 41h (r) hovf hf13 hf12 hf11 hf10 hf9 hf8 hcntl 42h (r) hf7 hf6 hf5 hf4 hf3 hf2 hf1 hf0 vcnth 43h (r) vovf vf11 vf10 vf9 vf8 vcntl 44h (r) vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 hvctr0 40h (w) c1 c0 nohins hbpl vbpl hvctr2 42h (w) selft stf1 stf0 rt1 rt0 ste hvctr3 43h (w) clpeg clppo clpw2 clpw1 clpw0 intflg 48h (r/w) hprchg vprchg hplchg vplchg hfchg vfchg vsync inten 49h (w) ehpr evpr ehpl evpl ehf evf evsync
myson technology mtv212m64i (rev 0.9) revision 0.9 - 23 - 2000/11/17 electrical parameters 1. absolute maximum ratings at: ta= 0 to 70 o c, vss=0v name symbol range unit maximum supply voltage vdd -0.3 to +6.0 v maximum input voltage vin -0.3 to vdd+0.3 v maximum output voltage vout -0.3 to vdd+0.3 v maximum operating temperature topg 0 to +70 o c maximum storage temperature tstg -25 to +125 o c 2. allowable operating conditions at: ta= 0 to 70 o c, vss=0v name symbol min. max. unit supply voltage vdd 4.5 5.5 v input "h" voltage vih1 0.4 x vdd vdd +0.3 v input "l" voltage vil1 -0.3 0.2 x vdd v operating freq. fopg - 15 mhz 3. dc characteristics at: ta=0 to 70 o c, vdd=5.0v, vss=0v name symbol condition min. typ. max. unit output "h" voltage, open drain pin voh1 ioh=0ua 4 v output "h" voltage, 8051 i/o port pin voh2 ioh=-50ua 4 v output "h" voltage, cmos output voh3 ioh=-4ma 4 v output "l" voltage vol iol=5ma 0.45 v active 18 24 ma idle 1.3 4.0 ma power supply current idd power-down 50 80 ua rst pull-down resistor rrst vdd=5v 150 250 kohm pin capacitance cio 15 pf 4. ac characteristics at: ta=0 to 70 o c, vdd=5.0v, vss=0v name symbol condition min. typ. max. unit crystal frequency fxtal 12 mhz pwm dac frequency fda fxtal=12mhz 46.875 94.86 khz hs input pulse width thipw fxtal=12mhz 0.3 8 us vs input pulse width tvipw fxtal=12mhz 3 us hsync to hblank output jitter thhbj 5 ns h+v to vblank output delay tvvbd fxtal=12mhz 8 us vs pulse width in h+v signal tvcpw fxtal=12mhz 20 us sda to scl setup time tdcsu 200 ns
myson technology mtv212m64i (rev 0.9) revision 0.9 - 24 - 2000/11/17 sda to scl hold time tdch 100 ns scl high time tsclh 500 ns scl low time tscll 500 ns start condition setup time tsu:sta 500 ns start condition hold time thd:sta 500 ns stop condition setup time tsu:sto 500 ns stop condition hold time thd:sto 500 ns t dch t dcsu t t t t t t su :sta hd :sta hd :sto su :sto sckl sckh data interface timing (i 2 c)
myson technology mtv212m64i (rev 0.9) revision 0.9 - 25 - 2000/11/17 package dimension 1. 40-pin pdip 600 mil 2. 42 pin sdip unit: mm dimension in mm symbol min nom max a 3.937 4.064 4.2 a1 1.78 1.842 1.88 b1 0.914 1.270 1.118 d 36.78 36.83 36.88 e1 13.945 13.970 13.995 f 15.19 15.240 15.29 eb 15.24 16.510 17.78 0 7.5 15 15.494mm +/- 0.254 13.868mm +/- 0.102 16.256mm +/- 0.508 0.254m m +/-0.102 5 o ~7 0 6 o +/- 3 o 52.197mm +/-0.127 15.494mm +/-0.254 2.540mm 0.457mm +/-0.127 1.270mm +/-0.254 1.981mm +/-0.254 3.81mm +/-0.127 1.778mm +/-0.127 0.254mm (min.) 3.302mm +/-0.254 13.868mm +/-0.102 16.256mm +/-0.508 0.254mm +/-0.102 5 o ~7 0 6 o +/-3 o
myson technology mtv212m64i (rev 0.9) revision 0.9 - 26 - 2000/11/17 3. 44 pin plcc unit: pin #1 hole 0.653 +/-0.003 0.690 +/-0.005 0.690 +/-0.005 0.653 +/-0.003 0.045*45 0 0.180 max. 0.020 min. 0.610 +/-0.02 0.500 0.070 0.070 7 0 typ. 0.010 0.050 typ. 0.013~0.021 typ. 0.026~0.032 typ. ordering information standard configurations: prefix part type package type rom size (k) mtv 212m n: pdip s: sdip v: plcc 64i part numbers: prefix part type package type rom size (k) mtv 212m n 64i mtv 212m s 64i mtv 212m v 64i

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